CMOS Analog IC Review Part I

2.4 MOS Device Models

MOS Device Capacitances

The overlap capacitance per unit width between gate and drain/source is denoted by C_ov. If the device is off, C_GD = C_GS = C_ovW, C_GB = C₁ in series with C₂, where

C₁ = WLC_ox is the oxide capacitance between the gate and the channel, and

C₂ = WL√[qε_siN_sub/(4Φ_F)] is the depletion capacitance between the channel and the substrate.

In deep triode region, i.e., V_DS ≈ 0, then C_GD = C_GS = WLC_ox/2 + WC_ov.

In saturation region, C_GD ≈ WC_ov, C_GS = 2WL_effC_ox/3 + WC_ov due to channel pinch-off. 

C_GB is usually neglected in the triode and saturation regions.

 

MOS Small-Signal Model

Due to channel-length modulation, drain current varies with the drain-source voltage. This effect can be modeled by a resistor tied between D and S:

r_O = ∂V_DS/∂_ID = 1/[(1/2)μ_nC_ox(W/L)(V_GS – V_TH)²λ] ≈ 1/(λI_D).

To model the bulk potential influence, a current source with value gmbVbs is connected between D and S. In saturation region,

g_mb = ∂I_D/∂V_BS = μ_nC_ox(W/L)(V_GS – V_TH)(-∂V_TH/∂V_BS), where

-∂V_TH/∂V_BS = γ/[2√(2Φ_F + V_SB)]